In integrated circuit microcomputers, memory circuits accessed by a processing unit are included. Such memory circuits typically have a parallel output in response to an address. The parallel output may be comprised of eight bits which may be called byte-wide. The memory circuits used in a microcomputer system include both random access memories (RAMs) and read only memories (ROMs). In some circumstances elements of both ROMs and RAMs are desired in response to a single address. For example, it may be desirable for some of the bits of a byte to be of a known logic state (ROM) and others to be changeable (RAM).
One of the problems associated with having a byte in memory be both ROM and RAM, is that during a write cycle excessive current may be drawn by the ROM bits. This can occur if a logic state opposite to that of the ROM bit is presented to the ROM bit while the row is enabled, which may occur during a write cycle. One solution to this problem has been to provide a separate word line for the ROM bits which can only be activated during a read cycle. This prevents the ROM bits from drawing current during a write cycle. This extra word line disadvantageously requires space, making the memory larger. Additionally, some additional circuitry is required to ensure that the extra word line is activated only during a read cycle, again increasing size.